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TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 1 post office box 655303 ? dallas, texas 75265 supports both fdm full rate (g.992.1) and g.lite (g.992.2) adsl applications integrated line driver for tx and line receiver for rx integrated tx/rx filter, pgas, and equalizer coexists with hpna devices (version 1.0 and 2.0) 14-bit integrated a/d and d/a converters 1.104 (g.lite)/2.208 (full rate) mhz update rate for the rx channel 276/552 khz update rate for the tx channel integrated voltage compensated crystal oscillator (vcxo) dac and digital phase-lock loop (dpll) ?150 dbm/hz for analog input referred noise floor direct single serial interface to tis c5000 or c6000 dsp families for both data and control two general-purpose i/o pins and four general-purpose digital outputs integrated auxiliary amplifiers for system flexibility software and hardware power-down modes power dissipation ? 1.4 w with line driver across 50- ? load delivering 12.3 dbm power to the line 3.3-v and 12-v supply (line driver) power supplies industrial temperature range (?40 c to 85 c) 64-pin pap package (powerpad ? ) description the TLFD600pap is a high-speed, programmable, analog front end for customer premise equipment (cpe) modems that supports g.lite (g.992.2) and full rate (g.992.1) adsl applications and incorporates both the codec and line drivers and receiver. the codec also coexists with home phoneline networking alliance (hpna)-devices, with the ability to work together with up to three hpna devices connected to the same line. the device performs transmit encoding (d/a conversion), receive decoding (a/d conversion), transmit and receive filtering functions, receive equalizer, and programmable gain amplifications (pga). the device also incorporates a voltage compensated crystal oscillator (vcxo) dac, dpll, line driver, and receiver for tx and rx channels which reduces the number of system components. two auxiliary amplifiers are provided, on-chip, for additional onboard filtering and amplification with additional off-chip passive components. the receive channel has an update rate of 1.104 msps in the g.lite mode and 2.208 msps in the full rate mode. the transmit channel has an update rate of 276 ksps and 552 ksps. a simple serial interface on the digital side reduces system component count. both data and control share the same serial port. the interface can connect directly to the ti c6000 and c5000 families of dsp chips. the device operates using 3.3-v and 12-v supply lines (12 v is used for the on-chip tx line driver) and is packaged in a single 64-pin pap (powerpad ? ) package. it is characterized for operation from ? 40 c to 85 c. copyright ? 2000, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. powerpad is a trademark of texas instruments.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 2 post office box 655303 ? dallas, texas 75265 pinout 12 3 gpio1 dvss_rx dvdd_rx gpio0 clk2out clk1out pllsel mclkin/pllclkin dv ss dv ss dv dd clkout_en clk1sel dvss_io dvdd_io sdx 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 4 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 amp1outp amp1inm amp1inp amp1outm avdd_rx avss_rx rxinp rxinm amp2outm amp2inp amp2inm amp2outp avss_driver driveroutm avdd_driver driveroutp 5678 gpo3 avdd_rx 47 46 45 44 43 48 42 ana_tst avdd_ref avss_ref rxbandgap refp refm vmid_adc modesel pwrdwn reset sclk txoutp txoutm avdd_tx avss_tx txbandgap compdac1 40 39 38 41 910111213 37 36 driverinp gpo5 35 34 33 14 15 16 sdr fsr fsx gpo4 avss_rx gpo2 v vcxo_cntl driverinm pap package (top view) compdac2 ss dv ss
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 3 post office box 655303 ? dallas, texas 75265 functional block diagram tx dac fsr fsx sdr sdx sclk 276 ksps/ 552 ksps digital hpf digital lpf 25.875 khz 138 khz 14 bit 4.416 msps tx lpf 138 khz paa ld rx lpf 1104 ksps/ 2208 ksps adc pga lpf equalizer pga hpf pga 14 bit 4.416 msps 0 to 9 db (1 db/step) rx pga3 552 khz/ 1104 khz 180 khz 0 to 25 db/mhz 5 db/mhz step 0 to 30 db (3 db/step) rx pga2 ? 9 to +9 db @ 6 db/step +9 to 30 db @ 3 db/step rx cpga (see note) aux amplifiers (2) general purpose i/o internal reference clock generator vcxo vcxo dac 0 to ? 24 db ( ? 1 db/step) tx pga vcxo mclkin clk1out/ clk2out clk1sel/ clkout_en refm/refp vmid_adc txbandgap/ rxbandgap internal clock gpio0-gpio1 gpo2-gpo5 ampinp/ ampinm ampoutp/ ampoutm rxinp/ rxinm driveroutp/ driveroutm driverinp/ driverinm txoutp/ txoutm 552 khz/ 1104 khz tx line driver 35.328 mhz digital loopback analog loopback hpf 180 khz dpll pllsel serial interface data and control note: the cpga gain range setting is related to the external components (r and c) that are connected to rxinp/m. refer to the re ceiver channel section for details.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 4 post office box 655303 ? dallas, texas 75265 terminal functions terminal i/o description name no. i/o description amp1inm amp2inm 50 59 i auxiliary amplifier 1 and 2 negative input amp1inp amp2inp 51 58 i auxiliary amplifier 1 and 2 positive input amp1outm amp2outm 52 57 o auxiliary amplifier 1 and 2 negative output amp1outp amp2outp 49 60 o auxiliary amplifier 1 and 2 positive output ana_tst 46 i external resistor connection input. a 15-k ? ( 5%) resistor must be connected between ana_tst and analog ground. avdd_driver 63 i analog power supply for tx driver (12 v) avdd_ref 45 i reference analog supply avdd_rx 38, 53 i rx channel filter analog supply avdd_tx 5 i tx channel analog supply avss_driver 61 i tx driver analog supply return (analog ground) avss_ref 44 i reference analog supply return (analog ground) avss_rx 39, 54 i rx channel filter analog supply return (analog ground) avss_tx 6 i tx channel analog supply return (analog ground). clk1out 27 o generates clock of frequency mclkx4/n, where n is 7 or 9. value of n is selected by clk1sel. clk2out 28 o generates clock of frequency mclkx4/34.5. clk1sel 20 i selects whether n = 7 or 9 for clk1out. for clk1sel = 0, n = 6. clkout_en 21 i enable clk1out and clk2out when clkout_en is high. the default state of clkout_en is low. compdac1 8 i tx channel decoupling cap input a. add a 1- f ceramic capacitor to analog power supply. compdac2 9 i tx channel decoupling cap input b. add a 1- f ceramic capacitor to analog power supply. driverinm 2 i tx channel driver negative input. a 0.1- f capacitor is needed when it connects to txoutm. driverinp 1 i tx channel driver positive input. a 0.1- f capacitor is needed when it connects to txoutp. driveroutm 62 o tx channel driver negative output driveroutp 64 o tx channel driver positive output dv dd 22 i digital power supply dvdd_io 18 i power supply for digital i/o buffer dvdd_rx 30 i rx channel digital power supply dv ss 23, 24, 37 i digital ground dvss_io 19 i digital i/o buffer supply return (digital ground) dvss_rx 31 i rx channel digital supply return (digital ground) fsx 16 o serial port frame sync transmit signal fsr 15 o serial port frame sync receive signal gpio0 gpio1 29 32 i/o general-purpose i/o gpo2 ? 5 33 ? 36 o general-purpose output mclkin/pllclkin 25 i master clock input for normal mode (use off-chip vcxo) and dpll (use fix input clock and change clock phase by control register) mode. the required input clock frequency is 35.328 mhz 50 ppm.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 5 post office box 655303 ? dallas, texas 75265 terminal functions (continued) terminal i/o description name no. i/o description modesel 10 i mode selection. modesel = 0 enable full rate mode. modesel = 1 enable g.lite mode. the default state of this pin is low. the chip goes with the setting of the register programming, if the configuration is different with this pin. pllsel 26 i dpll mode selection. pllsel = 1 will enable dpll mode. the default state of this pin is low. pwrdwn 11 i power-down pin. when pwrdwn is pulled low, the device goes into power-down mode. refm 41 o voltage reference filter negative output. there are two capacitors, with values of 10 f and 0.1 f, connected in parallel to analog ground. the nominal dc voltage at this terminal is 0.5 v. refp 42 o voltage reference filter positive output. there are two capacitors, with values of 10 f and 0.1 f, connected in parallel to analog ground. the dc voltage at this terminal is 2.5 v. reset 12 i device reset input pin. initializes all of the device ? s internal registers to their default values when reset is pulled low. rxbandgap 43 o rx channel bandgap filter node. this terminal is provided for decoupling of the 1.5-v band gap reference. there are two capacitors, with values of 10 f and 0.1 f, connected in parallel to analog ground. this node should not be used as a voltage source. rxinm 56 i rx channel stage negative input. this pin should not be directly connected. refer to receive channel for configuration. rxinp 55 i rx channel stage positive input. this pin should not be directly connected. refer to receive channel for configuration. sclk 13 o serial port shift clock (for both transmit and receive) sdr 14 i serial data receive sdx 17 o serial data transmit txbandgap 7 o tx channel band gap filter node. this terminal is provided for decoupling of the 1.5-v band gap reference. there are two capacitors, with values of 10 f and 0.1 f, connected in parallel to analog ground. this node should not be used as a voltage source. txoutp 3 o tx channel positive output txoutm 4 o tx channel negative output vcxo_cntl 47 o dac output to control off-chip vcxo vmid_adc 40 o decoupling vmid for adc. add a 10- f and a 0.1- f capacitor between this pin and analog ground. v ss 48 i substrate. connect to analog ground detailed description transmit channel the transmitter channel is powered by a high performance dac. this is a 4.416 mhz, 14-bit dac that provides 16x over-sampling to reduce the dac noise. a band pass filter limits the output of the transmitter from 28.875 khz to 138 khz. a programmable attenuation with a range of 24 db, in 1 db step size, drives the output into the on-chip adsl line driver (ac-coupling is needed). the 25.875-khz digital high pass filter (hpf) can be bypassed by register programming. the interface transfer rate is either 276 khz or 552 khz, controlled by register programming. the 138-khz low pass filter edge is programmable and is controlled by bit d4 of fmr register. d4=0 selects 138-khz ( 3.5%) pole, while d4=1 selects a 125-khz ( 3.5%) pole. for details of register programming, see register programming section. the output spectrum of the dac complies with the nonoverlapped psd mask specified in the itu standard g.992.2 for g.lite application and g.992.1 for full rate application.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 6 post office box 655303 ? dallas, texas 75265 transmit channel(continued) the line driver is also integrated in the tx channel. it helps optimize system components, board size, and cost. the driver is powered by a 12-v, supply and has a fixed gain of 15.7 db. this provides a maximum drive of 18.2 vp-p differential output when the input is 3 vp-p (maximum input range). thus, a transformer with 1:2 ratio is needed for adsl modem application. the minimum load that the driver can drive is 33 ? , thus, making the part coexist with up to 3 hpna devices connected to the same line. the line driver has separate input and output pins. this gives flexibility to add additional filters in the transmit path. the line driver can be powered down by register programming. the txoutp and txoutm pins must be ac-coupled to the driverinp and driverinm through 0.1- f capacitors, as the common mode voltage on the pin pairs are different (1.5 vdc on txoutp/m and 6 vdc on driverinp/m). they must not be dc-coupled. receive channel the receiver channel consists of a coarse programmable gain amplifier (cpga), analog high-pass and low-pass filters, two programmable gain amplifiers, adc, and a digital filter. in addition, it adds an equalizer to obtain maximum system performance. the receive signal is processed in a fully differential way. the adc in the receiver channel is a 4.416-mhz, 14-bit converter. the interface transfer rate is either 1104 khz or 2208 khz, depending on the mode at operation. 1104 khz is used for g.lite mode, and 2208 khz is used for full rate mode. the mode can be selected either by pin 10 (modesel) or register programming. the related cutoff frequency of analog and digital filters is also changed with the mode selection. the high-pass analog filter is used to reject the near end echo and maximize the dynamic range of the adc. the high-pass filter edge is programmable and is controlled by bit d2 of fmr register. d2 = 0 selects a 180-khz ( 3.5%) pole, while d2 = 1 selects a 168-khz ( 3.5%) pole. after the high-pass filtering stage, the receiver channel has two pgas. a 552-khz/1104-khz low-pass filter with a 25-db shape equalizer goes after them and antialiases the analog signal before it goes through the adc. the rx low pass filter is also designed to reject the out-of-band hpna signal. next is a fine gain adjustment pga of 0 to 9 db, in 1-db steps. all the rx pgas and equalizer are controlled via the register programming. external components are required to implement cpga function. suggested components and connection are shown in the figure 1. r = 732 ? c = 680 pf r = 732 ? c = 680 pf rxinp rxinm figure 1. external components for rxinp and rxinm the configuration of figure 1 gives the following setting for cpga: ? 9db to 9db in 6 db/steps and 9 db to 30 db in 3 db/steps. the cpga gain range is controlled by external resistors (732 ? shown in figure 1). the cut-off frequency of the hpf is controlled by external resistors (r) and capacitors (c). to keep the cutoff frequency of the first hpf unchanged, r c need to be constant.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 7 post office box 655303 ? dallas, texas 75265 receive channel (continued) for example: if r = 2063 ? , the external capacitor (c) needs to be 240 pf. the gain setting for cpga changes to the following range: ? 18 db to 0 db in 6 db/steps and 0 db to 21 db in 3 db/steps. the 9 db shifting is calculated by using the following equation: 20 log 2063 732 9db the linearity of the external capacitors and inductors is very important to the whole rx channel performance. capacitors of npo grade or better need to be used. clock control-vcxo a 12-bit, serial dac is used to control the external 35.328-mhz vcxo (voltage control oscillator) that provides the system clock to the codec. two 8-bit registers, (each 2s complement) vcrm and vcrl, are used to generate the 12-bit control code. this implies using two 8-bits to obtain a 12-bit code. the vcrm register occupies the most significant 8 bits in the 12-bit code and the lower 4 bits of the vcrl register (vcrl[3:0]) are used for the low 4 bits of the 12-bit code. the internal dac register is updated only when vcrl is programmed. table 1 shows some representative analog outputs. table 1. vcxo dac digital-analog mapping operation hex result analog output comments vcrm[7:0] 2 4 + vcrl[3:0] 0x800 0 v min scale 0x801 ? v just above min 0xfff 2047 ? v just below mid 0x000 2048 ? v mid scale 0x001 2049 ? v just above mid 0x7fe 4094 ? v just below max 0x7ff 4095 ? v max scale where step-size, ? = (3/4095) v. 1. the analog output is computed as follows: ((vcrm[7:0] 2 4 + vcrl[3:0]) + 2048(decimal)) ? . 2. step-size ? is computed as follows: 0 x 800 ( ? 2048 decimal) is 0 v and 0x7ff (2047 decimal) is 3 v. thus, ? = (3 ? 0) / (2047 ? ( ? 2048)) v = (3/4095) v clock generation the clock generation block provides the necessary clocks for the different functional blocks on the board with minimum skew and jitters. this is closely dependent on the performance of the external vcxo. the external vcxo specification is: 3.3-v supply 35.328 mhz 50 ppm minimum duty cycle is 60/40 (50/50 is the best) the on-chip clocks are shown in table 2. clk1out and clk2out can be used as general clock sources, or they can be disabled if they are not used.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 8 post office box 655303 ? dallas, texas 75265 clock generation (continued) table 2. clock description frequency (mhz) clock clkout_en = 1 symmetry clk1sel = 0 clk1sel = 1 sclk 35.328 35.328 50/50 clk1out 20.187 15.701 43/57 for 20.187 44/56 for 15.701 clk2out 4.096 4.096 49/51 serial interface the serial interface on the TLFD600pap will connect gluelessly to the c5000 or c6000 families of dsps from texas instruments. the serial interface operates at 35.328 mhz. the serial port is made up of five signals: sclk, fsx, fsr, sdx, and sdr. a typical connection diagram is shown in figure 2. clkr clkx fsx fsr dx dr sclk fsr fsx sdr sdx dsp TLFD600pap figure 2. typical serial port connection the serial port utilizes a primary/secondary scheme to transfer conversion data and control register data (command). a primary transfer is used to transfer conversion data. a secondary transfer is used to transfer control data when requested by the host processor. the host processor requests a secondary transfer by using the lsb of the sdr data of the primary transfer. a value of 1 indicates a secondary transfer request. once the secondary request is made and the primary transfer has completed, a secondary fsr pulse is transmitted to the host processor to indicate the beginning of the secondary transfer. the secondary fsr signal arrives 48 sclks after the host processor request. each bit is read/written at the rising edge of sclk clock. data bit mappings and example data transfers are shown in table 3. table 3. sdr lsb control function control bit d0 control bit function 0 no secondary transfer requested 1 secondary transfer requested
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 9 post office box 655303 ? dallas, texas 75265 primary transfer data mapping the data bit mapping of a primary transfer is shown in figure 3. d15 ? d2 bits of the sdr data stream are dac data. d1 is unused. d0 is the secondary transfer request bit. when a 1 is written to d0, the host is requesting a secondary data transfer. in the sdx data stream, d15 ? d2 contain the adc conversion data. d1 and d0 can be configured to reflect the values of gpio0 and gpio1, when they are configured as inputs. d1 and d0 will contain zeroes if they are not configured to reflect their corresponding gpio pin value, or if the gpio pin is configured as an output. to configure d1 and d0 to reflect the gpio values, the proper bit in the control register needs to be set. d15 ? d2 x d0 secondary transfer request dac data d15 ? d2 d1 d0 gpio1 and gpio0 status a/d data sdr sdx gpio1 gpio0 figure 3. primary transfer data bit mapping secondary transfer data mapping secondary serial communication is used to configure the device. the data bit mapping for a secondary transfer is shown in figure 4. the d14 ? d10 bits of the sdr data, from the host, are the address bits of the control register involved in the transfer. bits d7 ? d0 contain the data to the register. d15 needs to be set to zero all the time. a control register read-back function is not supported. as a result, there is no secondary fsx or sdx. 0 sdr (write) a4 a3 a2 a1 a0 d9 d8 d7 register address don ? t care data to the register d15 d0 figure 4. secondary transfer data bit mapping example data transfers figure 5 and 6 show the timing relationship for sclk, fsx, sdx, fsr, and sdr in a primary or secondary communication. the update rate for tx and rx are controlled by pin configuration and register programming. the timing sequence for this operation is as follows: 1. fs is brought high and remains high for one sclk period, then goes back low. 2. a 16-bit word is transmitted from the adc (sdx) and a 16-bit word is received for dac conversion (sdr). figure 5 through 14 show the timing relationship of the data transfers with and without secondary request.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 10 post office box 655303 ? dallas, texas 75265 example data transfers (continued) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sclk (output) fsx (output) sdx (output) t3 t2 t1 t1: fsx is detected by dsp t2: TLFD600pn send data t3: dsp latch data figure 5. example data transfers (TLFD600pap to dsp) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sclk (output) fsr (output) sdr (input) t3 t2 t1 t1: fsr is detected by dsp t2: dsp send data t3: TLFD600pn latch data figure 6. example data transfers (dsp to TLFD600pap) 128 sclks 48 sclks 16 sclks p p p p p p p s fsr fsx sdr sdx data data data data data data command zeroes zeroes zeroes don ? t care don ? t care data zeroes figure 7. example data transfers with secondary request in g.lite and normal tx mode (276 ksps for tx/fsr and 1104 ksps for rx/fsx)
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 11 post office box 655303 ? dallas, texas 75265 example data transfers (continued) 128 sclks 32 sclks 16 sclks p p p p p p p fsr fsx sdr sdx data data data data data data data zeroes zeroes zeroes zeroes don ? t care figure 8. example data transfers without secondary request in g.lite and normal tx mode (276 ksps for tx/fsr and 1104 ksps for rx/fsx) 64 sclks 48 sclks 16 sclks s fsr fsx sdr sdx data data data data data data command zeroes zeroes zeroes don ? t care don ? t care data zeroes pp p p p p p p data figure 9. example data transfers with secondary request in g.lite and double tx mode (552 ksps for tx/fsr and 1104 ksps for rx/fsx)
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 12 post office box 655303 ? dallas, texas 75265 example data transfers (continued) 64 sclks 32 sclks 16 sclks p fsr fsx sdr sdx data data data data data data data zeroes zeroes zeroes zeroes don ? t care p p p p p p p data don ? t care figure 10. example data transfers without secondary request in g.lite and double tx mode (552 ksps for tx/fsr and 1104 ksps for rx/fsx) 128 sclks 48 sclks 16 sclks p p p p p p p s fsr fsx sdr sdx data data data command don ? t care don ? t care data data data data data data data data p p p p figure 11. example data transfers with secondary request in full rate and normal tx mode (276 ksps for tx/fsr and 2208 ksps for rx/fsx)
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 13 post office box 655303 ? dallas, texas 75265 example data transfers (continued) 128 sclks 32 sclks 16 sclks p p fsr fsx sdr sdx data data don ? t care data data data data data data data data data data p p p p p p p pp figure 12. example data transfers without secondary request in full rate and normal tx mode (276 ksps for tx/fsr and 2208 ksps for rx/fsx) 48 sclks 16 sclks p p p s fsr fsx sdr sdx data data data data data data data data data data data data command p p p p p p p p don ? t care don ? t care p data 64 sclks figure 13. example data transfers with secondary request in full rate and double tx mode (552 ksps for tx/fsr and 2208 ksps for rx/fsx)
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 14 post office box 655303 ? dallas, texas 75265 example data transfers (continued) 64 sclks 16 sclks p p p fsr fsx sdr sdx data data data data data data data data data data data data p p p p p p p p p data don ? t care don ? t care figure 14. example data transfers without secondary request in full rate and double tx mode (552 ksps for tx/fsr and 2208 ksps for rx/fsx) general-purpose i/o port (gpio) the general-purpose i/o port provides input/output pins for control of external circuitry or reading status of external devices. gpio0 and gpio1 can be configured through the control register as input/output. gpo2 to gpo5 are output only. the configuration of gpio0 and gpio1 pins are controlled by the auxgprc register and are reflected in the gpr-d register. the status of gpio0 and gpio1 can also be mapped into the lower 2 bits of the sdx (that is, from codec to dsp) data stream during primary data transfers. to map the values of gpio0 and gpio1 into the lower 2 bits of the sdx adc data stream, set the appropriate bit in the main control register (mcr). each i/o output is capable of driving 2 ma. reference system the integrated reference provides the needed voltage and current to the internal analog blocks. it is also brought out to external pins for noise decoupling. auxiliary amplifiers there are two high-performance auxiliary operational amplifiers on - chip for additional onboard filtering and amplification at the appropriate configuration. each op - amp is differential input and differential output and can be disabled by register programming. the typical specifications are as follows: dc gain: 126 db bandwidth: 116 mhz psrr: 100 db at dc, 70 db at 1 mhz and 40 db at 4 mhz input common mode: 1.65 - v at 3.3 - v power supply amplifier input referred noise: 2 nv/ hz
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 15 post office box 655303 ? dallas, texas 75265 power down both hardware and software power-down modes are provided. some function blocks can be powered down individually according to the control register setting. a logic-zero on the pwrdwn pin will completely shut down the codec. device initialization time reset must be held at least 20 s after power up. to reset the reference circuit and registers requires 100 ms. when the chip is woken up from hardware power-down mode, it takes 100 ms to reset the reference circuit before the chip works in normal mode. when the chip is woken up from software power-down mode, only 20 s is needed before valid data comes out (reference must be kept on). register values will not change in either wake-up operation. dpll description as an alternative to the vcxodac and vcxo, an off - chip crystal oscillator (xo) followed by an on - chip digital pll is also implemented. see figure 15 for the internal functional block diagram. the input clock (35.328 mhz) goes to a programmable frequency - divider to generate the sampling clock for the adc and dac. by changing the divide ratio, the phase of sampling clock for adc and dac channels can be adjusted. therefore, setting the pllsel (pin 26) high to enable the dpll mode. the default value of register nco_def is 64, and it can only be changed internally. with the 35.328 - mhz input clock, the output frequency of pll is 4 x 35.328 = 141.312 mhz. to obtain an adc clock (adcclk) of 4.416 mhz, the divide ratio (controlled by register nco_def and nco_delta) needs to be 32. increasing or decreasing this ratio (for example, 32.5 or 31.5) temporally can effect the phase of 4.416 - mhz sampling clock. see the following example for details. + pll (x4) nco_def 2 nco_div_delay nco_delta [7:4] nco_delta [3:0] mclkin/ pllclkin clock to converter figure 15. dpll internal functional block diagram example: mclkin/pllclkin = 35.328 mhz. with nco_def defaults at 64, 4.416 - mhz clock is provided to the adc converter by the following equation: 4.416 35.328 4 64 2 if nco_delta [7:4] is set to ? 1, nco_delta [3:0] is set to 3, and nco_div_dly is set to 2 (nco_div_dly should be the last register to be programmed), the internal divider will change to 63 three times. the change of the internal adc clock will be reflected at the 55 th , 71 st , and 87 th sclk cycles after nco_div_dly is programmed. the serial clock normally has a high of 14 ns and a low of 14 ns. the duty cycle of the sclk changes to 14 ns / 7 ns (14 ns / 21 ns if nco_delta [7:4] = +1) during those jittering sclk cycles. reprogramming of the register nco_div_delay is needed if further adjustment is required.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 16 post office box 655303 ? dallas, texas 75265 dpll description (continued) the position of the first jittering sclk cycle is calculated by using the following equation: ( nco_div_dly [7 : 0] 1 ) 16 7 the following jittering sclks will separate by 16 sclk from the first one if nco_delta[3:0] is more than one. figures 16 and 17 shows the timing of sclk at the following setting: nco_delta [7:4] = ? 1 nco_delta [3:0] = 2 nco_div_delay = 2 64 sclks 16 sclks p p p fsr fsx sdr sclk data p p p p p p p p p data don ? t care don ? t care s p the 9th sclk duty cycle change to 14ns(1) and 7ns(0) 15th 0 secondary command request command to program nco_div_delay start counting figure 16. dpll operation example (fsr = 552 khz and fsx = 2208 khz) note: the situation will be the same for fsr = 276 khz
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 17 post office box 655303 ? dallas, texas 75265 dpll description (continued) 64 sclks 16 sclks p p p fsr fsx sdr sclk data p p p p p data don ? t care don ? t care s 15th 0 start counting secondary command request command to program nco_div_delay figure 17. dpll operation example (fsr = 552 khz and fsx = 1104 khz) note: the situation will be the same for fsr = 276 khz.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 18 post office box 655303 ? dallas, texas 75265 register programming the codec registers are listed below. all registers are 8-bits wide. bits not defined in table 4 are reserved for future use. these reserved bits need to be written as zero during register programming. table 4. register programming register default name address a4 ? a0 default value function bcr 00001 00000000 d2: bypass tx digital hp filter d3: echo mode: echo sdr data on sdx d5: force all digital outputs high d6: force all digital outputs low d7: power-down tx line driver pcr-rx1 00010 00000000 d[5:2] = rxpga3[3:0]; fine gain, 0 to 9 db, 1 db step pcr-rx2 00011 00001011 d[7:4] = rxpga2[3:0]; 0 to 30 db, 3 db step d[3:0] = rxcpga[3:0]; ? 9 to 9 db at 6 db/step and 9 to 30 db at 3 db/step. pcr-tx 00100 00000000 d[4:0] = tx paa[4:0]; 0 to ? 24 db, ? 1 db/step eqr 00101 00000000 d[2:0] = eq[2:0]; 0 to 25 db/mhz, 5 db/mhz per step vcr-m 00110 00000000 d[7:0] = vcxo dac control bit[11:4] vcr-l 00111 00000000 d[3:0] = vcxo dac control bit[3:0]. d[7:4] must be zero not used 01000 00000000 reserved gpr-d 01001 00000000 d[7:0] = general-purpose i/o data register data fmr 01010 00000000 d0: g.lite/full rate mode selection. (0 = same as pin default, 1 = opposite of pin default. see modesel in pin description section) d1:tx update rate selection; 276 ksps (d1 = 0) or 512 ksps (d1=1) d2:reserved d3:reserved d4:bandwidth selection for tx channel (0 = 138 khz, 1 = 125 khz) auxgprc 01011 00001100 d0=1: enable auxiliary amplifier 2 d1=1: enable auxiliary amplifier 1 d[3:2] = gpio0 and gpio1 i/o control (0 = output, 1 = input) nco_def 01100 01000000 d[6:0] = default nco divide number nco_div_dly 01101 00000000 d[7:0] number of samples (or frames), from current secondary transfer, after which effect of delta will occur. this register should be the last register to be programmed in dpll mode. nco_delta 01110 00000000 d[7:4] = delta from default for first sample of data frame ( ? 1 through 1) d[3:0] = number of times the internal nco divider remains changed after register nco_div_dly is programmed. mcr 01111 00000000 d0: s/w power down main reference d1: s/w power down tx channel with reference still on d2: s/w power down rx channel with reference still on d3: s/w power down vcxo dac with reference still on d4: s/w reset d5: analog loop back d6: digital loop back d7: enable gpio0 and 1 to show in sdx primary data. note: the gain range of cpga is related to the external resistor. the gain setting shown above is under the condition of r = 732 ? and c = 680 pf. refer to the receiver channel section for details.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 19 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted) ? supply voltage, avdd to agnd, dvdd to dgnd ? 0.3 v to 4.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage, avdd_driver to agnd ? 0.3 v to 15 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog input voltage range to agnd see note 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital input voltage range ? 0.3 v to 4.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating virtual junction temperature range, t j ? 40 c to 120 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: the analog input pins (rxinp/rxinm) are virtual ac ground in the normal application mode. recommended operating conditions power supply min typ max unit supply voltage, v cc driver analog supply (av dd _driver) 12 v analog supply (avdd_rx, avdd_ref, avdd_tx) 3 3.3 3.6 v digital supply (dvdd, dvdd_io, dvdd_rx) 3 3.3 3.6 v analog inputs min typ max unit full scale range (single ended) at point a and b (see figure 20) rx cpga = ? 9 db 4.2 v p ? p digital inputs min typ max unit high - level input voltage, v ih 2.4 v low - level input voltage, v il 0.6 v high - level input current, i ih 10 a low - level input current, i il 10 a digital outputs min typ max unit high - level output voltage, v oh 2.4 v low - level output voltage, v ol 0.6 v clock inputs min typ max unit input clock frequency 35.328 mhz input clock high time 13.5 14.15 15 ns
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 20 post office box 655303 ? dallas, texas 75265 electrical characteristics, t a = 25 c, analog power supplies = 3.3 v, digital power supplies = 3.3 v, avdd_driver = 12 v, f clkin = 35.328 mhz (unless otherwise noted) rx channel parameter test conditions min typ max unit hi g h-pass fmr [d2] = 1 162 168 174 signal bandwidth g filter fmr [d2] = 0 174 180 186 khz signal bandwidth low p ass filter g.lite mode 552 khz low - pass filter full rate mode 1104 g.lite mode 1. 4.3125 khz spaced tones from 138 ? 552 khz 2. 422.625 khz tone is missing 60 missing tone power ratio (mtpr) full rate mode 1. 4.3125 khz spaced tones from 138 ? 1104 khz 2. 422.625 khz tone is missing 60 db group delay distortion g.lite or full rate mode 10 s cpga ? 0.5 0.5 gain step error pga2 g.lite or full rate mode ? 0.5 0.5 db pga3 ? 0.5 0.5 psrr g.lite mode see note 2 ? 70 db psrr full rate mode see note 2 ? 70 db g.lite mode cpga 21 db pga2 30 db pga3 9 db ? 150 input reference noise floor full rate mode cpga = 21 db , pga2 = 30 db , pga3 = 9 db , equalizer = 0 db ? 150 dbm/hz cmrr g.lite and full rate mode 60 db note 2: inject single tone signal (267.375 khz) at 200 mvp-p to analog power supplies and measure 267.375 khz tones at rx output .
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 21 post office box 655303 ? dallas, texas 75265 electrical characteristics, t a = 25 c, analog power supplies = 3.3 v, digital power supplies = 3.3 v, avdd_driver = 12 v, f clkin = 35.328 mhz (unless otherwise noted) (continued) tx channel (tx line driver is not included) parameter test conditions min typ max unit low p ass filter fmr [d4] = 0 133 138 143 khz signal bandwidth low - pass filter fmr [d4] = 1 121 125 129 khz high-pass filter 25.875 khz mtpr 1. 4.3125khz spaced tones from 25.875 to 138 khz 2. 81.9375 khz tone is missing 70 db group delay distortion 10 s paa gain step error ? 0.5 0.5 db psrr see note 2 ? 70 db out-of-band noise see note 3 ? 150 dbm/hz notes: 2. inject single tone signal (267.375 khz) at 200 mvp-p to analog power supplies and measure 267.375 khz tones at rx outpu t. 3. send multitone signal (25.875 to 138 khz at 4.3125 khz/step) at full scale output level and measure signal level beyond 276 k hz at txoutp/m. tx driver (avdd_driver = 12 v) parameter test conditions min typ max unit output voltage swing input signal is 138 khz @ 3 v p-p differential at driverinp/m, r l = 50 ? 18.2 v p-p output current 220 output short circuit protection current limit 300 ma tsnr input 3 v p-p differential @ 138 khz at driverinp/m 85 db driverinp/m input impedance 600 ? vcxo dac parameter test conditions min typ max unit resolution 12 bits dnl differential nonlinearity 1 lsb inl integral nonlinearity 4 lsb monotonicity 12 bits offset error ? 100 100 mv output compliance voltage maximum code input with load = 50 k ? 3 v output load 50 k ? power dissipation parameter test conditions min typ max unit analog (tx line driver is not included) all avdd = 3.3 v 620 695 mw digital all dvdd = 3.3 v 150 165 mw fully operational without tx line driver 770 860 mw tx driver quiescent, avdd_driver = 12 v 510 570 mw tx driver ? 47 dbm/hz dmt signal (par = 17 db) on 50 - ? load, (avdd_driver = 12 v) 610 690 mw fully operational with driver 1380 1530 mw h/w power down 160 250 mw
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 22 post office box 655303 ? dallas, texas 75265 electrical characteristics, t a = 25 c, analog power supplies = 3.3 v, digital power supplies = 3.3 v, avdd_driver = 12 v, f clkin = 35.328 mhz (unless otherwise noted) (continued) reference voltage parameter min typ max unit refp 2.4 2.5 2.6 v txbandgap, rxbandgap 1.4 1.5 1.6 v refm 0.4 0.5 0.6 v vmid_adc 1.47 v timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) serial port (see figures 18 and 19) parameter min typ max unit t d(1) delay time, fsx goes high after sclk 4 ns t d(2) delay time, fsx goes low after sclk 4 ns t d(3) delay time, sdx valid after sclk 4 ns t d(4) delay time, fsr goes high after sclk 4 ns t d(5) delay time, fsr goes low after sclk 4 ns t su set up time, sdr ready before sclk 6 ns t h hold time, sdr keep active after sclk 2 ns fsx (output) sclk (output) sdx (ouput) t d(1) t d(2) t d(3) figure 18. serial interface timing (tx channel) fsr (output) sclk (output) sdr (input) t (su) t d(4) t d(5) t h figure 19. serial interface timing (rx channel)
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 23 post office box 655303 ? dallas, texas 75265 application information driveroutm driveroutp driverinp driverinm txoutm txoutp rxinm rxinp fsr fsx sdr sdx sclk 62 64 1 2 4 3 56 55 15 16 14 17 13 0.1 f 0.1 f 732 ? 680 pf 732 ? 680 pf ana_tst compdac2 compdac1 txbandgap rxbandgap refm refp 46 9 8 7 43 41 42 15 k ? 1 f1 f 10 f 0.1 f 10 f 0.1 f 0.1 f 10 f 10 f 0.1 f vcc_3.3 v dvss dvss dvss dvss_io dvss_rx avss_driver avss_rx avss_rx avss_tx avss_ref v ss pwrdwn reset 37 24 23 19 31 61 39 54 6 44 48 11 12 5 k ? 5 k ? dvdd_3.3 v clk2out clk1out mclkin vcxo_cntl gpo2 ? 5 gpio1 gpio0 dd dv dvdd_rx dvdd_io avdd_rx avdd_rx avdd_tx avdd_ref avdd_driver 28 27 25 47 33 ? 36 32 29 22 30 18 63 38 53 5 45 avcc_3.3 v avcc_12 v dvcc_3.3 v a b figure 20. typical chip configuration
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 24 post office box 655303 ? dallas, texas 75265 programming information bcr ? bypass control register address: 00001b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 pdtxdr dig_low dig_high reserved echo bptxhp reserved reserved table 5. bcr control table bit name d7 d6 d5 d4 d3 d2 d1 d0 description pdtxdr 1 power down tx line driver dig_low 1 force all digital outputs low dig_high 1 force all digital outputs high reserved 0 reserved bit. see note 4 echo 1 echo sdr data on sdx. see note 5 bptxhp 1 bypass tx hp filter (25.875 khz) reserved 0 reserved reserved 0 reserved notes: 4. all reserved bits should be programmed as 0 during normal application. 5. echo mode allows for a quick verification of whether the TLFD600 serial interface is working. it sends back the data from the input data buffer to the output data buffer and does not go through the rx or tx channel. pcr-rx1 ? programmable gain control register 1 for rx channel address: 00010b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved rxpga3[3] rxpga3[2] rxpga3[1] rxpga3[0] reserved reserved table 6. pcr-rx1 gain table bit name d7 d6 d5 d4 d3 d2 d1 d0 description reserved 0 reserved reserved 0 reserved rxpga3[3] rxpga3[2] rxpga3[1] rxpga3[0] 0 0 0 0 rx pga3 = 0 db 0 0 0 1 rx pga3 = 1 db 0 0 1 0 rx pga3 = 2 db 0 0 1 1 rx pga3 = 3 db 0 1 0 0 rx pga3 = 4 db 0 1 0 1 rx pga3 = 5 db 0 1 1 0 rx pga3 = 6 db 0 1 1 1 rx pga3 = 7 db 1 0 0 0 rx pga3 = 8 db 1 0 0 1 rx pga3 = 9 db ? ? ? ? see note 6 for all other combinations reserved 0 reserved reserved 0 reserved note 6: performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 25 post office box 655303 ? dallas, texas 75265 programming information pcr-rx2 ? programmable gain control register 2 for rx channel address: 00011b contents at reset: 00001011b d7 d6 d5 d4 d3 d2 d1 d0 rxpga2[3] rxpga2[2] rxpga2[1] rxpga2[0] rxcpga1[3] rxcpga1[2] rxcpga1[1] rxcpga1[0] table 7. pcr-rx2 gain table bit name d7 d6 d5 d4 d3 d2 d1 d0 description rxpga2[3] rxpga2[2] rxpga2[1] rxpga2[0] 0 0 0 0 rx pga2 = 0 db 0 0 0 1 rx pga2 = 3 db 0 0 1 0 rx pga2 = 6 db 0 0 1 1 rx pga2 = 9 db 0 1 0 0 rx pga2 = 12 db 0 1 0 1 rx pga2 = 15 db 0 1 1 0 rx pga2 = 18 db 0 1 1 1 rx pga2 = 21 db 1 0 0 0 rx pga2 = 24 db 1 0 0 1 rx pga2 = 27 db 1 0 1 0 rx pga2 = 30 db ? ? ? ? see note 6 rxcpga1[3] rxcpga1[2] rxcpga1[1] rxcpga1[0] 0 0 0 0 rxcpga = 9 db 0 0 0 1 rxcpga = 12 db 0 0 1 0 rxcpga = 15 db 0 0 1 1 rxcpga = 18 db 0 1 0 0 rxcpga = 21 db 0 1 0 1 rxcpga = 24 db 0 1 1 0 rxcpga = 27 db 0 1 1 1 rxcpga = 30 db 1 0 0 0 invalid 1 0 0 1 rxcpga = 3 db 1 0 1 0 rxcpga = ? 3 db 1 0 1 1 rxcpga = ? 9 db ? ? ? ? see note 6 note 6. performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 26 post office box 655303 ? dallas, texas 75265 programming information pcr-rtx ? programmable attenuation control register for tx channel address: 00100b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved txpaa[4] txpaa[3] txpaa[2] txpaa[1] txpaa[0] table 8. pcr-tx attenuation table bit name d7 d6 d5 d4 d3 d2 d1 d0 description reserved 0 reserved reserved 0 reserved reserved 0 reserved txpaa[4] txpaa[3] txpaa[2] txpaa[1] txpaa[0] 0 0 0 0 0 tx paa = 0 db 0 0 0 0 1 tx paa = ? 1 db 0 0 0 1 0 tx paa = ? 2 db 0 0 0 1 1 tx paa = ? 3 db 0 0 1 0 0 tx paa = ? 4 db 0 0 1 0 1 tx paa = ? 5 db 0 0 1 1 0 tx paa = ? 6 db 0 0 1 1 1 tx paa = ? 7 db 0 1 0 0 0 tx paa = ? 8 db 0 1 0 0 1 tx paa = ? 9 db 0 1 0 1 0 tx paa = ? 10 db 0 1 0 1 1 tx paa = ? 11 db 0 1 1 0 0 tx paa = ? 12 db 0 1 1 0 1 tx paa = ? 13 db 0 1 1 1 0 tx paa = ? 14 db 0 1 1 1 1 tx paa = ? 15 db 1 0 0 0 0 tx paa = ? 16 db 1 0 0 0 1 tx paa = ? 17 db 1 0 0 1 0 tx paa = ? 18 db 1 0 0 1 1 tx paa = ? 19 db 1 0 1 0 0 tx paa = ? 20 db 1 0 1 0 1 tx paa = ? 21 db 1 0 1 1 0 tx paa = ? 22 db 1 0 1 1 1 tx paa = ? 23 db 1 1 0 0 0 tx paa = ? 24 db ? ? ? ? ? see note 6 note 6. performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 27 post office box 655303 ? dallas, texas 75265 programming information equalizer shape control register address: 00101b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved reserved eqs[2] eqs[1] eqs[0] table 9. eqr shape table bit name d7 d6 d5 d4 d3 d2 d1 d0 description reserved 0 reserved reserved 0 reserved reserved 0 reserved reserved 0 reserved reserved 0 reserved eqs[2] eqs[1] eqs[0] 0 0 0 rx eq = 0 db/mhz 0 0 1 rx eq = 5 db/mhz 0 1 0 rx eq = 10 db/mhz 0 1 1 rx eq = 15 db/mhz 1 0 0 rx eq = 20 db/mhz 1 0 1 rx eq = 25 db/mhz ? ? ? see note 6 for all other combinations note 6. performance of the codec for invalid combination of bits is not guaranteed and such combinations should not be used. vcr-m ? vcxo dac control register msb address: 00110b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 vcrmm[7] vcrm[6] vcrm[5] vcrm[4] vcrm[3] vcrm[2] vcrm[1] vcrm[0] vcr-l ? vcxo dac control register lsb address: 00111b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 vcrl[3] vcrl[2] vcrl[1] vcrl[0]
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 28 post office box 655303 ? dallas, texas 75265 programming information gpr-d ? gpio data register address: 01001b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved gpod[5] gpod[4] gpod[3] gpod[2] gpod[1] gpod[0] table 10. gpio control table bit name d7 d6 d5 d4 d3 d2 d1 d0 description reserved 0 reserved reserved 0 reserved gpod[5] 0/1 gpo5 = 0/1 gpod[4] 0/1 gpo4 = 0/1 gpod[3] 0/1 gpo3 = 0/1 gpod[2] 0/1 gpo2 = 0/1 gpiod[1] 0/1 gpio1 = 0/1 when gpio1 is configured as output. see note 7. gpiod[0] 0/1 gpio0 = 0/1 when gpio1 is configured as output. see note 7. note 7: it is recommended to write zeroes to gpio1 and gpio0 if they are configured as inputs. fmr ? frequency mode register address: 01010b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved sltxbw reserved slrxbw dbltxs togmod table 11. fmr control table bit name d7 d6 d5 d4 d3 d2 d1 d0 description reserved 0 reserved reserved 0 reserved reserved 0 reserved sltxbw 1 tx lpf bandwidth 125 khz sltxbw 0 tx lpf bandwidth 138 khz reserved 0 reserved slrxbw 0 reserved dbltxs 1 tx fsr sampling at 552 ksps dbltxs 0 tx fsr sampling at 276 ksps togmod 1 work mode (g.lite/full rate) opposite of that selected by modesel pin togmod 0 work mode (g.lite/full rate) as selected by modesel pin note 8: table 12 shows the effect of modesel pin (pin 10) and togmod bit (fmr[0]).
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 29 post office box 655303 ? dallas, texas 75265 programming information table 12. mode selection table inputs output modesel pin (pin 10) togmod bit (fmr[0]) resultant mode comments 0 0 full rate rx analog and digital lpf at 1104 khz 0 1 g.lite rx analog and digital lpf at 552 khz 1 0 g.lite rx analog and digital lpf at 552 khz 1 1 full rate rx analog and digital lpf at 1104 khz auxgprc ? auxiliary amplifier and gpr direction control register address: 01011b contents at reset: 00001100b d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved gpioc[1] gpioc[0] amp1en amp2en table 13. auxgprc control table bit name d7 d6 d5 d4 d3 d2 d1 d0 description reserved 1 reserved bit reserved 1 reserved bit reserved 1 reserved bit reserved 1 reserved bit gpioc[1] 0 configure pin gpio1 as output gpioc[1] 1 configure pin gpio1 as input gpioc[0] 0 configure pin gpio0 as output gpioc[0] 1 configure pin gpio0 as input amp1en 0 enable on-chip auxiliary amplifier 1 amp2en 0 enable on-chip auxiliary amplifier 2 nco_def ? numerically controlled oscillator default value register address: 01100b contents at reset: 01000000b (64 decimal) d7 d6 d5 d4 d3 d2 d1 d0 reserved ncodef[6] ncodef[5] ncodef[4] ncodef[3] ncodef[2] ncodef[1] ncodef[0] note 9: nco_def register should never be written to. it always holds the default value of 64.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 30 post office box 655303 ? dallas, texas 75265 programming information nco_div_delay ? numerically controlled oscillator delay control register address: 01101b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 ncdly[7] ncdly[6] ncdly[5] ncdly[4] ncdly[3] ncdly[2] ncdly[1] ncdly[0] table 14. nco value table bit name d7 d6 d5 d4 d3 d2 d1 d0 description ncdly[7:0] 0 0 0 0 0 0 0 0 invalid 0 0 0 0 0 0 0 1 adclk jittered 1 sample clocks (of adclk) after write into the nco_div_delay register ? ? ? ? ? ? ? ? adclk jittered 2 to 255 sample clocks (of adclk) after write into the nco_div_delay register note 10: this register is also the only means of communicating to the codec that the adclk must be jittered. thus, not writing a value implies that jitter will not take place even if other registers have non-default values. this register does not remember its value. all other registers store their values unless reset. nco_delta ? numerically controlled oscillator delta value register address: 01110b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 ncdel[3] ncdel[2] ncdel[1] ncdel[0] ncrpt[3] ncrpt[2] ncrpt[1] ncrpt[0] table 15. nco_delta delta and repeat table bit name d7 d6 d5 d4 d3 d2 d1 d0 description ncdel[3:0] 0 0 0 0 delta = 0 0 0 0 1 delta = 1 1 1 1 1 delta = ? 1 ncrpt[3:0] 0 0 0 0 repeat = 0 0 0 0 1 repeat = 1 ? ? ? ? 1 1 1 1 repeat = 15 note 11: n = ncodef[6:0] + delta, and adcclk = (35.328 4)/(n/2). example: 1. if ncdel[3:0] = 0000 (delta = 0), then n = 64. and adcclk = (35.328 4)/(n/2). 2. if ncdel[3:0] = 0001 (delta = 1), then n = 65. and adcclk = (35.328 4)/(n/2).
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 31 post office box 655303 ? dallas, texas 75265 programming information mcr ? master control register address: 01111b contents at reset: 00000000b d7 d6 d5 d4 d3 d2 d1 d0 gp12en dlben alben swrst vcdacpd rxpd txpd swrefpd table 16. mcr control table bit name d7 d6 d5 d4 d3 d2 d1 d0 description gp12en 1 show gpio 1, 2 in sdx primary dlben 1 enable digital loop back alben 1 enable analog loop back swrst 1 software reset vcdacpd 1 power down vcxo dac rxpd 1 power down rx channel txpd 1 power down tx channel swrefpd 1 power down main reference notes: 12. analog loop back means looping back of the analog tx output to the rx input (the rx high-pass filters are bypassed). t his way the codec can be tested without needing external analog sources. refer to block diagram for signal path. 13. digital loop back means looping back the digital rx output to the tx input. refer to block diagram for signal path.
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 32 post office box 655303 ? dallas, texas 75265 principles of operation ? 100 ? 120 ? 160 ? 200 0 0.2 0.4 0.6 0.8 1 1.2 gain ? db ? 40 ? 20 f ? frequency ? mhz tx channel composite response 0 1.4 1.6 ? 60 ? 80 ? 140 ? 180 figure 21. tx channel filter response (dhpf is enabled) ? 100 ? 140 ? 160 ? 200 0 0.05 0.1 0.15 gain ? db ? 60 ? 20 f ? frequency ? mhz tx channel composite response (zoomed in) 0 0.2 0.25 ? 40 ? 80 ? 120 ? 180 figure 22. tx channel filter response (zoom in)
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 33 post office box 655303 ? dallas, texas 75265 principles of operation ? 100 ? 120 ? 160 ? 200 0 5 10 15 gain ? db ? 60 ? 20 f ? frequency ? khz tx channel hpf response (zoomed in) 0 20 25 ? 40 ? 80 ? 140 ? 180 30 figure 23. tx channel hpf response (zoom in) 0 0 ? 50 ? 100 ? 150 ? 200 12345678910 f ? frequency ? mhz gain ? db receive channel response with different equalizer settings figure 24. receive channel frequency responses with different equalizer slope settings (full rate)
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 34 post office box 655303 ? dallas, texas 75265 principles of operation 50 0 0 ? 50 ? 100 ? 150 ? 200 ? 250 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 f ? frequency ? mhz gain ? db transmit channel response figure 25. rx channel response with different equalizer settings (g.lite mode) ? 100 ? 120 ? 160 ? 200 0 0.05 0.1 0.15 gain ? db ? 60 ? 20 f ? frequency ? mhz rx channel hpf1 + hpf2 response (zoomed in) 0 0.2 0.25 ? 40 ? 80 ? 140 ? 180 figure 26. rx channel hpf response (zoom in)
TLFD600 adsl codec with integrated line driver and receiver slas280b ? may 2000 ? revised november 2000 35 post office box 655303 ? dallas, texas 75265 mechanical data pap (s-pqfp-g64) powerpad ? plastic quad flatpack thermal pad (see note d) 0,13 nom 0,25 0,45 0,75 seating plane 4147702/a 01/98 gage plane 0,17 0,27 33 16 48 1 7,50 typ 49 64 sq 9,80 1,05 0,95 11,80 12,20 1,20 max 10,20 sq 17 32 0,08 0,50 m 0,08 0 ? 7 0,15 0,05 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. d. the package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. this pad is electrically and thermally connected to the backside of the die and possibly selected leads. e. falls within jedec ms-026 powerpad is a trademark of texas instruments.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its products to the specifications applicable at the time of sale in accordance with ti ? s standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer ? s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such products or services might be or are used. ti ? s publication of information regarding any third party ? s products or services does not constitute ti ? s approval, license, warranty or endorsement thereof. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated ti product or service, is an unfair and deceptive business practice, and ti is not responsible nor liable for any such use. resale of ti ? s products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service, is an unfair and deceptive business practice, and ti is not responsible nor liable for any such use. also see: standard terms and conditions of sale for semiconductor products. www.ti.com/sc/docs/stdterms.htm mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2001, texas instruments incorporated

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